The invention relates to a decoding device for a stream of successively receivable code symbols which are protected against errors by a first and a second Reed-Solomon code. Each of the symbols of a code word of the second code being assigned to an respective code word of the first code. The decoding device comprises a first input for code symbols of the first code and associated reliability information. A storage means stores any updated symbols of the first code until at least all symbols of a code word of the second code are present together. A first arithmetic means forms the syndrome symbols for any code word of a code. A second arithmetic means are fed by the first arithmetic means in order to form, on the basis of the code symbols received, the syndrome symbols found and, if desired, also on the basis of reliability information associated with the latter code symbols, updating information which consists of locator information and error information for the presentation of data symbols of the second code, whether or not updated by means of the updating information, on a user output. Flag processing means are provided for adding, on the basis of reliability information associated with a code, word of the first code and the processing result of the second arithmetic means on a code word of the first code, signalization information which has been modified or not to symbols to be included in a code word of the second code. A device of this kind is known from the previous Netherlands Patent Application No. 8200207 corresponding to U.S. Pat. No. 4,477,903 in the name of Applicant. According to the present state of the art, code symbols may be provided with an invalidity bit upon demodulation. This bit can be used in various ways. When the code word contains an excessive number of flagged code symbols, all symbols of the relevant code word are provided with an invalidity bit. On the other hand, when a symbol provided with an invalidity bit is not corrected, if desired, all symbols of the relevant code word are also provided with an invalidity bit. Thirdly, within given limits the invalidity bit can be used as an error locator, so that the correction capability of the code as a whole is increased. The inventors of the present invention have found that such a strategy where the invalidity bit indicates either correct or incorrect code symbol is not very flexible and also results in an excessively restricted use of the possibilities of the code. It is an object of the invention to increase the flexibility and correction capability of the code by utilizing multivalent flag information per code symbol.